module SYSCLKS
  Interface ( CLK,RESET -> PE,NE,PRE_PE,PRE_NE,CLK_O );
Title 'system timing generator'

" Difference:
" Delay PE and NE and PRE*'s for 1clk against CLK_O.
" Then, any signals which's made from them are delaied. 
" & x20 ver

Declarations
" ---------- external interface pins ---------
CLK,RESET PIN;
PE,NE,PRE_PE,PRE_NE,CLK_O PIN istype 'com';

" ---------- internal nodes ---------
CNT4..CNT0 node istype 'reg';
PRE_DIV node istype 'reg';
CNT = [CNT4..CNT0];

" 3210FEDCBA9876543210
" _~_~_~_~_~_~_~_~_~_~ PRE_DIV
" ~~~~~~~~~~__________ CNT0
" __~~~~~~~~~~________ CNT1
" ____~~~~~~~~~~______ CNT2
" ______~~~~~~~~~~____ CNT3
" ________~~~~~~~~~~__ CNT4
" __________~~~~~~~~~~ CLK_O
"          *           PRE_PE
"           *          PE
"                    * PRE_NE
" *                    NE

Equations

PRE_PE=CNT0 & CNT4 & PRE_DIV;
PRE_NE=!CNT0 & !CNT4 & PRE_DIV;
PE=!CNT0 & CNT1 & !PRE_DIV;
NE=CNT0 & !CNT1 & !PRE_DIV;
CLK_O=!CNT0;

CNT.CLK=CLK;
CNT.ACLR=!RESET;
PRE_DIV.CLK=CLK;
PRE_DIV.ACLR=!RESET;
PRE_DIV:=!PRE_DIV;

CNT.CE=PRE_DIV;
CNT0.D=!CNT4 # (CNT0 & !CNT3);
CNT1.D=CNT0;
CNT2.D=CNT1;
CNT3.D=CNT2;
CNT4.D=CNT3;

end SYSCLKS